The present invention relates to a peripheral unit for a microprocessor system and, more particularly, to a peripheral unit which halts its operation and cancels the halt of its operation in response to the output of a microprocessor or external circuits.
FIG. 1 shows a block diagram of a conventional microprocessor system which is widely used.
A microprocessor (which is called a "CPU" below) as a main element in the microprocessor system is connected to memories or peripheral units via a data bus, an address bus, and a control bus. Recently, battery driving apparatus or many kinds of peripheral apparatus for a portable computer have been developed. In view of the construction or characteristics of the above apparatus, each of the apparatus is required to consume a little power, so that the microprocessor system is attempted to be constructed of CMOS (Complementary Metal Oxide Semiconductor) transistors.
The power consumption in the circuit constructed of the CMOS transistors is small. However, the current to be consumed in the activated condition is about 1,000- 10,000 times as large as the current to be consumed in the non-activated condition. The power consumption of the microprocessor system may be reduced by increasing a non-activate period and by decreasing an activated period to decrease unnecessary power consumption.
However, in the conventional microprocessor system, even when the microprocessor system is constructed of CMOS transistors, the peripheral units are kept in the operative condition, so that the power consumption of each of the peripheral units cannot be reduced.